1. Field of Technology
The present invention relates to a memory control apparatus which performs memory control by utilizing serial data, and to a serial memory which receives and outputs data in serial form.
2. Description of Prior Art
In the prior art, a type of serial EEPROM (electrically erasable programmable memory) is known whereby data are transferred between the memory and external circuits via a serial interface. Such a serial EEPROM basically consists of a memory array and a control circuit which performs functions whereby portions of an externally supplied input serial data stream which constitute control information (e.g., such as memory read or write instructions) are converted to parallel form and decoded, and whereby address and data portions of the input serial data are converted to parallel form and supplied to the memory array, and further whereby sets of parallel data which are read out from the memory array are converted to serial form.
The term xe2x80x9cmemoryxe2x80x9d alone is used herein to signify a device that is a combination of a control circuit and a memory array (i.e., array of memory cells) as described above, that is to say, a combination which may be formed on an integrated circuit chip as a single device.
Such a control circuit includes a start bit detection circuit which detects start bits that occur within the input serial data, and a shift register which (when a start bit has occurred) successively registers a set of serial data bits which succeed a start bit, to thereby convert each such set into parallel data form. The registering of successive input data bits in the shift register is performed under the control of (i.e., synchronized with) a clock signal, which will be referred to in the following as the operating clock signal, which is also externally supplied. Frames of input serial data are thereby converted to respective sets of parallel data. With such a control circuit, when the start bit detection circuit detects occurrence of a start bit in the input serial data stream, the shift register is set in operation to acquire the serial data. When a predetermined number of bits have been set into the shift register, the shifting operation is halted, to prevent overflow.
A specific example of such a control circuit is described in Japanese Patent HEI 4-114289. In that example, a counter is utilized, which counts up to a specific number of cycles of the operating clock signal. When a start bit is detected in the input serial data stream, supplying of the operating clock signal to the shift register is started, while at the same time the counter is set in operation. When the counter reaches the predetermined count value, the supplying of the operating clock signal to the shift register is halted, to thereby halt the operation of the shift register.
However since such a counter is large in circuit scale, incorporation of the counter results in the overall size of the control circuit becoming large. Furthermore, due to the fact that shift register control is implemented by using a counter, if a count error occurs due to the effects of noise, etc., then the count value will not correspond to the actual state of the shift register. Hence, errors in the operation of the control circuit may occur, as a result of the effects of noise.
Another problem of the prior art is as follows. The length of each of the instructions which serve to control the operation of an EEPROM should preferably be as short as possible, in order to minimize the circuit scale of the control circuit and to maximize the performance of the circuit which decodes these instructions. Such an instruction set may for example include instructions that are used for debugging, i.e., special instructions that will not normally be required. However if such special instructions are handled at the same level as the usual instructions (i.e., the instructions which are used to control the operation of the EEPROM under normal circumstances) then the processing performance for usual instructions will be lowered.
On the other hand, if the control circuit is to be configured such as to be capable of using variable-length instructions, so that special instructions can be conveyed by greater numbers of bits than usual instructions, then the circuit may be formed with an area that serves to handle the usual instructions and an extension area which is used to handle the special instructions. However in order to be able to handle such variable-length instructions, it is necessary for some way to be provided for notifying the memory control circuit of the instruction length. For example, additional control terminals might be provided to receive such notification information. However this results in the overall chip size being increased, when the control circuit is formed on an integrated circuit chip.
Moreover another problem arises when designing a control circuit which must handle such variable-length instructions. Specifically, the frame format for the sets of serial data that are sent to or transmitted from the memory will vary, in accordance with whether a usual instruction or a special instruction is conveyed. Thus, the shift register locations (stages) into which the bits of a usual instruction will be set will differ, depending upon whether the control circuit is designed to handle only usual instructions (and so does not have an extension region) or is designed to also handle variable-length instructions (and so has an extension region). As a result, the design of the decoder circuit which operates on the data held in the shift register will become complex, and the overall circuit scale will be increased.
It is an objective of the present invention to overcome the above problems of the prior art, by providing a memory control apparatus and a serial memory whereby the occurrence of operating errors due to electrical noise can be prevented while in addition the circuit scale can be small and the circuit power consumption can be low.
It is a further objective of the invention to provide such a memory control apparatus, configured such as to have a capability for expansion when necessary for handling variable-length instructions, with the bits expressing a usual instruction being always produced from one specific part of the control circuit, and without requiring the provision of additional terminals for receiving information notifying of variable-length instructions.
To achieve the above objectives, according to a first aspect, which relates to a memory which receives serial data conveying fixed-length instructions together with an operating clock signal that is synchronized with the serial data, with each instruction being expressed by a command data portion of a fixed-length data frame and with the command data portion being preceded by a start bit, the invention basically provides a memory control apparatus which incorporates serial data registering means having the following features. A shift register is provided, having a number of register stages that is identical to the frame length (i.e., number of bits of a command data portion, incremented by one), with the shift register being reset prior to setting a new set of data therein, i.e., each time that an operation such as instruction execution based on a received serial data frame has been completed. Specifically, each shift register stage is initialized to a logic level that is the inverse of that of the start bits. A start bit detection circuit generates a start bit detection signal when occurrence of a start bit is detected in the input serial data, and a clock control circuit enables supply of the operating clock signal, as a shift clock, to the shift register during an interval which extends from the point at which the start bit detection signal begins to be generated until the point at which the logic level of the MSB output of the shift register becomes inverted. That is to say, when a serial data frame is correctly received, the supply of the operating clock signal to the shift register is continued until all of the frame bits have been set into the shift register, with the start bit having thus been shifted into the MSB stage of the shift register.
In addition, an excess clock detection circuit is provided, which generates an excess clock detection signal in the event that at least one cycle of the operating clock signal is received after the aforementioned logic level inversion of the MSB output has occurred.
As a result, if electrical noise has been induced in the connecting lead which supplies the operating clock signal from an external source, and has caused at least one of the bits of a frame to be shifted into the shift register more than once during a single clock cycle (thereby causing the start bit to be set in the MSB stage of the shift register prematurely), so that one or more excess operating clock signal cycles are received after the logic level of the MSB output of the shift register has been inverted, this condition is immediately detected. In a described embodiment, an error control section responds to the excess clock detection signal by immediately resetting the shift register to the initialized state, so that no errors in controlling the memory array will occur.
In that way, it becomes unnecessary to utilize a counter circuit for controlling the supply of the operating clock signal to the shift register, so that the overall circuit scale can be minimized. In addition it becomes possible to eliminate any adverse effects of electrical noise which may be contained in the received operating clock signal.
More specifically, according to a first aspect, the invention provides a memory control apparatus having serial data registering means for outputting data to control a memory array, with the data registering means receiving serial data and a corresponding operating clock signal from an external source, in which the serial data registering means comprises:
start bit detection means, which generates a start bit detection signal when a start bit is received in the serial data,
a shift register controlled by the operating clock signal to register a number of bits of the serial data which is equal to the command data portion bit length incremented by one, and which is initialized such that logic levels of the outputs from the respective shift register stages are set as the inverse of the logic level of the start bits (i.e., the xe2x80x9c1xe2x80x9d state logic level) after a memory control operation using the output data from the shift register has been completed,
clock control circuit means functioning, during an interval extending from the start of generating the start bit detection signal until the logic level of the output from the MSB stage of the shift register is inverted to the start bit logic level (i.e., when the state of a received start bit is shifted into the MSB stage of the shift register), to supply the operating clock signal as a shift clock to the shift register, and
excess clock detection means responsive to occurrence of at least one cycle of the operating clock signal, subsequent to the inverting of the MSB logic level, for generating an excess clock detection signal.
According to a second aspect, the invention provides a memory control apparatus having serial data registering means performing a similar function to that described above, but which is capable of registering variable-length instructions. In that case, an instruction other than a usual instruction (i.e., a special instruction, which has a longer bit length than a usual instruction) is formed as one or more command data portions, each preceded by a start bit, which consecutively follow a command data portion that has the same bit length as a usual instruction. A plurality of control blocks are provided, each of which performs the various functions described above, other than the start bit detection function, and contains a shift register capable of registering a bit length which is identical to a specific corresponding command data portion of a usual instruction or of a special instruction.
A separate start bit detection circuit supplies the start bit detection signal to a first-stage control block (which registers the bits of a usual instruction, or of the leading portion of a special instruction). Thus, the first-stage control block operates as described above, however if a special instruction is received (so that corresponding operating clock cycles continue to be received on completion of setting data into the shift register of that control block) the output signal from the excess clock detection signal of the first-stage control block is applied to enable supply of the operating clock signal to the shift register of the second-stage control block. Third and subsequent stage control blocks are similarly controlled, by the excess clock detection signal from the preceding-stage control block.
In that way it becomes possible to ensure, for example, that the bits of a usual instruction will always be outputted from one specific shift register, irrespective of how many control blocks are incorporated, i.e., irrespective of the number of different lengths of instruction which the memory control apparatus is designed to be capable of handling.